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PIC is a family of modified Harvard architecture
microcontrollers made by Microchip Technology, derived from the
PIC1650[1][2][3] originally developed by General Instrument's
Microelectronics Division. The name PIC initially referred to
"Peripheral Interface Controller".[4][5]
PICs are popular with both industrial developers and hobbyists alike due to their low cost, wide availability, large user base, extensive collection of application notes, availability of low cost or free development tools, and serial programming (and re-programming with flash memory) capability. They are also commonly used in educational programming as they often come with the easy to use 'pic logicator' software.
Contents
1 History
2 Core architecture
2.1 Data space (RAM)
2.2 Code space
2.3 Word size
2.4 Stacks
2.5 Instruction set
2.6 Performance
2.7 Advantages
2.8 Limitations
2.9 Compiler development
3 Family core architectural differences
3.1 Baseline core devices (12 bit)
3.2 ELAN Microelectronics clones (13 bit)
3.3 Mid-range core devices (14 bit)
3.4 Enhanced mid-range core devices (14 bit)
3.5 PIC17 high end core devices (16 bit)
3.6 PIC18 high end core devices (16 bit)
3.7 PIC24 and dsPIC 16-bit microcontrollers
3.8 PIC32 32-bit microcontrollers
4 Device variants and hardware features
4.1 Variants
4.2 Trends
4.3 Part number suffixes
4.4 PIC clones
5 Development tools
6 Device programmers
6.1 PICKit 2 clones and open source
7 Debugging
7.1 Software emulation
7.2 In-circuit debugging
7.3 In-circuit emulators
8 See also
9 References
10 External links
History
Various older (EPROM) PIC microcontrollers
The original PIC was built to be used with General Instrument's new 16-bit CPU, the CP1600. While generally a good CPU, the CP1600 had poor I/O performance, and the 8-bit PIC was developed in 1975 to improve performance of the overall system by offloading I/O tasks from the CPU. The PIC used simple microcode stored in ROM to perform its tasks, and although the term was not used at the time, it shares some common features with RISC designs.
In 1985, General Instrument spun off their microelectronics division and the new ownership cancelled almost everything — which by this time was mostly out-of-date. The PIC, however, was upgraded with internal EPROM to produce a programmable channel controller and today a huge variety of PICs are available with various on-board peripherals (serial communication modules, UARTs, motor control kernels, etc.) and program memory from 256 words to 64k words and more (a "word" is one assembly language instruction, varying from 12, 14 or 16 bits depending on the specific PIC micro family).
PIC and PICmicro are registered trademarks of Microchip Technology. It is generally thought that PIC stands for Peripheral Interface Controller, although General Instruments' original acronym for the initial PIC1640 and PIC1650 devices was "Programmable Interface Controller".[4] The acronym was quickly replaced with "Programmable Intelligent Computer".[5]
The Microchip 16C84 (PIC16x84), introduced in 1993, was the first[citation needed] Microchip CPU with on-chip EEPROM memory. This electrically erasable memory made it cost less than CPUs that required a quartz "erase window" for erasing EPROM.
Core architecture
The PIC architecture is characterized by its multiple attributes:
Separate code and data spaces (Harvard architecture).
A small number of fixed length instructions
Most instructions are single cycle execution (2 clock cycles, or 4 clock cycles in 8-bit models), with one delay cycle on branches and skips
One accumulator (W0), the use of which (as source operand) is implied (i.e. is not encoded in the opcode)
All RAM locations function as registers as both source and/or destination of math and other functions.[6]
A hardware stack for storing return addresses
A small amount of addressable data space (32, 128, or 256 bytes, depending on the family), extended through banking
Data space mapped CPU, port, and peripheral registers
ALU status flags are mapped into the data space
The program counter is also mapped into the data space and writable (this is used to implement indirect jumps).
There is no distinction between memory space and register space because the RAM serves the job of both memory and registers, and the RAM is usually just referred to as the register file or simply as the registers.
Data space (RAM)
PICs have a set of registers that function as general purpose RAM. Special purpose control registers for on-chip hardware resources are also mapped into the data space. The addressability of memory varies depending on device series, and all PIC devices have some banking mechanism to extend addressing to additional memory. Later series of devices feature move instructions which can cover the whole addressable space, independent of the selected bank. In earlier devices, any register move had to be achieved via the accumulator.
To implement indirect addressing, a "file select register" (FSR) and "indirect register" (INDF) are used. A register number is written to the FSR, after which reads from or writes to INDF will actually be to or from the register pointed to by FSR. Later devices extended this concept with post- and pre- increment/decrement for greater efficiency in accessing sequentially stored data. This also allows FSR to be treated almost like a stack pointer (SP).
External data memory is not directly addressable except in some high pin count PIC18 devices.
Code space
The code space is generally implemented as ROM, EPROM or flash ROM. In general, external code memory is not directly addressable due to the lack of an external memory interface. The exceptions are PIC17 and select high pin count PIC18 devices.[7]
Word size
All PICs handle (and address) data in 8-bit chunks. However, the unit of addressability of the code space is not generally the same as the data space. For example, PICs in the baseline (PIC12) and mid-range (PIC16) families have program memory addressable in the same wordsize as the instruction width, i.e. 12 or 14 bits respectively. In contrast, in the PIC18 series, the program memory is addressed in 8-bit increments (bytes), which differs from the instruction width of 16 bits.
In order to be clear, the program memory capacity is usually stated in number of (single word) instructions, rather than in bytes.
Stacks
PICs have a hardware call stack, which is used to save return addresses. The hardware stack is not software accessible on earlier devices, but this changed with the 18 series devices.
Hardware support for a general purpose parameter stack was lacking in early series, but this greatly improved in the 18 series, making the 18 series architecture more friendly to high level language compilers.
Instruction set
A PIC's instructions vary from about 35 instructions for the low-end PICs to over 80 instructions for the high-end PICs. The instruction set includes instructions to perform a variety of operations on registers directly, the accumulator and a literal constant or the accumulator and a register, as well as for conditional execution, and program branching.
Some operations, such as bit setting and testing, can be performed on any numbered register, but bi-operand arithmetic operations always involve W (the accumulator), writing the result back to either W or the other operand register. To load a constant, it is necessary to load it into W before it can be moved into another register. On the older cores, all register moves needed to pass through W, but this changed on the "high end" cores.
PIC cores have skip instructions which are used for conditional execution and branching. The skip instructions are 'skip if bit set' and 'skip if bit not set'. Because cores before PIC18 had only unconditional branch instructions, conditional jumps are implemented by a conditional skip (with the opposite condition) followed by an unconditional branch. Skips are also of utility for conditional execution of any immediate single following instruction. It is possible to skip skip instructions. For example, the instruction sequence "skip if A; skip if B; C" will execute C if A is true or if B is false.
The 18 series implemented shadow registers which save several important registers during an interrupt, providing hardware support for automatically saving processor state when servicing interrupts.
In general, PIC instructions fall into 5 classes:
Operation on working register (WREG) with 8-bit immediate ("literal") operand. E.g. movlw (move literal to WREG), andlw (AND literal with WREG). One instruction peculiar to the PIC is retlw, load immediate into WREG and return, which is used with computed branches to produce lookup tables.
Operation with WREG and indexed register. The result can be written to either the Working register (e.g. addwf reg,w). or the selected register (e.g. addwf reg,f).
Bit operations. These take a register number and a bit number, and perform one of 4 actions: set or clear a bit, and test and skip on set/clear. The latter are used to perform conditional branches. The usual ALU status flags are available in a numbered register so operations such as "branch on carry clear" are possible.
Control transfers. Other than the skip instructions previously mentioned, there are only two: goto and call.
A few miscellaneous zero-operand instructions, such as return from subroutine, and sleep to enter low-power mode.
Performance
The architectural decisions are directed at the maximization of speed-to-cost ratio. The PIC architecture was among the first scalar CPU designs,[citation needed] and is still among the simplest and cheapest. The Harvard architecture—in which instructions and data come from separate sources—simplifies timing and microcircuit design greatly, and this benefits clock speed, price, and power consumption.
The PIC instruction set is suited to implementation of fast lookup tables in the program space. Such lookups take one instruction and two instruction cycles. Many functions can be modeled in this way. Optimization is facilitated by the relatively large program space of the PIC (e.g. 4096 × 14-bit words on the 16F690) and by the design of the instruction set, which allows for embedded constants. For example, a branch instruction's target may be indexed by W, and execute a "RETLW" which does as it is named - return with literal in W.
Interrupt latency is constant at three instruction cycles. External interrupts have to be synchronized with the four clock instruction cycle, otherwise there can be a one instruction cycle jitter. Internal interrupts are already synchronized. The constant interrupt latency allows PICs to achieve interrupt driven low jitter timing sequences. An example of this is a video sync pulse generator. This is no longer true in the newest PIC models, because they have a synchronous interrupt latency of three or four cycles.
Advantages
The PIC architectures have these advantages:
Small instruction set to learn
RISC architecture
Built in oscillator with selectable speeds
Easy entry level, in circuit programming plus in circuit debugging PICKit units available for less than $50
Inexpensive microcontrollers
Wide range of interfaces including I²C, SPI, USB, USART, A/D, programmable comparators, PWM, LIN, CAN, PSP, and Ethernet[8]
Limitations
The PIC architectures have these limitations:
One accumulator
Register-bank switching is required to access the entire RAM of many devices
Operations and registers are not orthogonal; some instructions can address RAM and/or immediate constants, while others can only use the accumulator
The following stack limitations have been addressed in the PIC18 series, but still apply to earlier cores:
The hardware call stack is not addressable, so preemptive task switching cannot be implemented
Software-implemented stacks are not efficient, so it is difficult to generate reentrant code and support local variables
With paged program memory, there are two page sizes to worry about: one for CALL and GOTO and another for computed GOTO (typically used for table lookups). For example, on PIC16, CALL and GOTO have 11 bits of addressing, so the page size is 2048 instruction words. For computed GOTOs, where you add to PCL, the page size is 256 instruction words. In both cases, the upper address bits are provided by the PCLATH register. This register must be changed every time control transfers between pages. PCLATH must also be preserved by any interrupt handler.[9]
Compiler development
While several commercial compilers are available, in 2008, Microchip released their own C compilers, C18 and C30, for the line of 18F 24F and 30/33F processors.
The easy to learn RISC instruction set of the PIC assembly language code can make the overall flow difficult to comprehend. Judicious use of simple macros can increase the readability of PIC assembly language. For example, the original Parallax PIC assembler ("SPASM") has macros which hide W and make the PIC look like a two-address machine. It has macro instructions like "mov b, a" (move the data from address a to address b) and "add b, a" (add data from address a to data in address b). It also hides the skip instructions by providing three operand branch macro instructions such as "cjne a, b, dest" (compare a with b and jump to dest if they are not equal).
Family core architectural differences
PICmiro chips have a Harvard architecture, and instruction words are unusual sizes. Originally, 12-bit instructions included 5 address bits to specify the memory operand, and 9-bit branch destinations. Later revisions added opcode bits, allowing additional address bits.
Baseline core devices (12 bit)
These devices feature a 12-bit wide code memory, a 32-byte register file, and a tiny two level deep call stack. They are represented by the PIC10 series, as well as by some PIC12 and PIC16 devices. Baseline devices are available in 6-pin to 40-pin packages.
Generally the first 7 to 9 bytes of the register file are special-purpose registers, and the remaining bytes are general purpose RAM. Pointers are implemented using a register pair: after writing an address to the FSR (file select register), the INDF (indirect f) register becomes an alias for the addressed register. If banked RAM is implemented, the bank number is selected by the high 3 bits of the FSR. This affects register numbers 16–31; registers 0–15 are global and not affected by the bank select bits.
Because of the very limited register space (5 bits), 4 rarely read registers were not assigned addresses, but written by special instructions (OPTION and TRIS).
The ROM address space is 512 words (12 bits each), which may be extended to 2048 words by banking. CALL and GOTO instructions specify the low 9 bits of the new code location; additional high-order bits are taken from the status register. Note that a CALL instruction only includes 8 bits of address, and may only specify addresses in the first half of each 512-word page.
Lookup tables are implemented using a computed GOTO (assignment to PCL register) into a table of RETLW instructions.
The instruction set is as follows. Register numbers are referred to as "f", while constants are referred to as "k". Bit numbers (0–7) are selected by "b". The "d" bit selects the destination: 0 indicates W, while 1 indicates that the result is written back to source register f. The C and Z status flags may be set based on the result; otherwise they are unmodified. Add and subtract (but not rotate) instructions that set C also set the DC (digit carry) flag, the carry from bit 3 to bit 4, which is useful for BCD arithmetic.</div>
PICs are popular with both industrial developers and hobbyists alike due to their low cost, wide availability, large user base, extensive collection of application notes, availability of low cost or free development tools, and serial programming (and re-programming with flash memory) capability. They are also commonly used in educational programming as they often come with the easy to use 'pic logicator' software.
Contents
1 History
2 Core architecture
2.1 Data space (RAM)
2.2 Code space
2.3 Word size
2.4 Stacks
2.5 Instruction set
2.6 Performance
2.7 Advantages
2.8 Limitations
2.9 Compiler development
3 Family core architectural differences
3.1 Baseline core devices (12 bit)
3.2 ELAN Microelectronics clones (13 bit)
3.3 Mid-range core devices (14 bit)
3.4 Enhanced mid-range core devices (14 bit)
3.5 PIC17 high end core devices (16 bit)
3.6 PIC18 high end core devices (16 bit)
3.7 PIC24 and dsPIC 16-bit microcontrollers
3.8 PIC32 32-bit microcontrollers
4 Device variants and hardware features
4.1 Variants
4.2 Trends
4.3 Part number suffixes
4.4 PIC clones
5 Development tools
6 Device programmers
6.1 PICKit 2 clones and open source
7 Debugging
7.1 Software emulation
7.2 In-circuit debugging
7.3 In-circuit emulators
8 See also
9 References
10 External links
History
Various older (EPROM) PIC microcontrollers
The original PIC was built to be used with General Instrument's new 16-bit CPU, the CP1600. While generally a good CPU, the CP1600 had poor I/O performance, and the 8-bit PIC was developed in 1975 to improve performance of the overall system by offloading I/O tasks from the CPU. The PIC used simple microcode stored in ROM to perform its tasks, and although the term was not used at the time, it shares some common features with RISC designs.
In 1985, General Instrument spun off their microelectronics division and the new ownership cancelled almost everything — which by this time was mostly out-of-date. The PIC, however, was upgraded with internal EPROM to produce a programmable channel controller and today a huge variety of PICs are available with various on-board peripherals (serial communication modules, UARTs, motor control kernels, etc.) and program memory from 256 words to 64k words and more (a "word" is one assembly language instruction, varying from 12, 14 or 16 bits depending on the specific PIC micro family).
PIC and PICmicro are registered trademarks of Microchip Technology. It is generally thought that PIC stands for Peripheral Interface Controller, although General Instruments' original acronym for the initial PIC1640 and PIC1650 devices was "Programmable Interface Controller".[4] The acronym was quickly replaced with "Programmable Intelligent Computer".[5]
The Microchip 16C84 (PIC16x84), introduced in 1993, was the first[citation needed] Microchip CPU with on-chip EEPROM memory. This electrically erasable memory made it cost less than CPUs that required a quartz "erase window" for erasing EPROM.
Core architecture
The PIC architecture is characterized by its multiple attributes:
Separate code and data spaces (Harvard architecture).
A small number of fixed length instructions
Most instructions are single cycle execution (2 clock cycles, or 4 clock cycles in 8-bit models), with one delay cycle on branches and skips
One accumulator (W0), the use of which (as source operand) is implied (i.e. is not encoded in the opcode)
All RAM locations function as registers as both source and/or destination of math and other functions.[6]
A hardware stack for storing return addresses
A small amount of addressable data space (32, 128, or 256 bytes, depending on the family), extended through banking
Data space mapped CPU, port, and peripheral registers
ALU status flags are mapped into the data space
The program counter is also mapped into the data space and writable (this is used to implement indirect jumps).
There is no distinction between memory space and register space because the RAM serves the job of both memory and registers, and the RAM is usually just referred to as the register file or simply as the registers.
Data space (RAM)
PICs have a set of registers that function as general purpose RAM. Special purpose control registers for on-chip hardware resources are also mapped into the data space. The addressability of memory varies depending on device series, and all PIC devices have some banking mechanism to extend addressing to additional memory. Later series of devices feature move instructions which can cover the whole addressable space, independent of the selected bank. In earlier devices, any register move had to be achieved via the accumulator.
To implement indirect addressing, a "file select register" (FSR) and "indirect register" (INDF) are used. A register number is written to the FSR, after which reads from or writes to INDF will actually be to or from the register pointed to by FSR. Later devices extended this concept with post- and pre- increment/decrement for greater efficiency in accessing sequentially stored data. This also allows FSR to be treated almost like a stack pointer (SP).
External data memory is not directly addressable except in some high pin count PIC18 devices.
Code space
The code space is generally implemented as ROM, EPROM or flash ROM. In general, external code memory is not directly addressable due to the lack of an external memory interface. The exceptions are PIC17 and select high pin count PIC18 devices.[7]
Word size
All PICs handle (and address) data in 8-bit chunks. However, the unit of addressability of the code space is not generally the same as the data space. For example, PICs in the baseline (PIC12) and mid-range (PIC16) families have program memory addressable in the same wordsize as the instruction width, i.e. 12 or 14 bits respectively. In contrast, in the PIC18 series, the program memory is addressed in 8-bit increments (bytes), which differs from the instruction width of 16 bits.
In order to be clear, the program memory capacity is usually stated in number of (single word) instructions, rather than in bytes.
Stacks
PICs have a hardware call stack, which is used to save return addresses. The hardware stack is not software accessible on earlier devices, but this changed with the 18 series devices.
Hardware support for a general purpose parameter stack was lacking in early series, but this greatly improved in the 18 series, making the 18 series architecture more friendly to high level language compilers.
Instruction set
A PIC's instructions vary from about 35 instructions for the low-end PICs to over 80 instructions for the high-end PICs. The instruction set includes instructions to perform a variety of operations on registers directly, the accumulator and a literal constant or the accumulator and a register, as well as for conditional execution, and program branching.
Some operations, such as bit setting and testing, can be performed on any numbered register, but bi-operand arithmetic operations always involve W (the accumulator), writing the result back to either W or the other operand register. To load a constant, it is necessary to load it into W before it can be moved into another register. On the older cores, all register moves needed to pass through W, but this changed on the "high end" cores.
PIC cores have skip instructions which are used for conditional execution and branching. The skip instructions are 'skip if bit set' and 'skip if bit not set'. Because cores before PIC18 had only unconditional branch instructions, conditional jumps are implemented by a conditional skip (with the opposite condition) followed by an unconditional branch. Skips are also of utility for conditional execution of any immediate single following instruction. It is possible to skip skip instructions. For example, the instruction sequence "skip if A; skip if B; C" will execute C if A is true or if B is false.
The 18 series implemented shadow registers which save several important registers during an interrupt, providing hardware support for automatically saving processor state when servicing interrupts.
In general, PIC instructions fall into 5 classes:
Operation on working register (WREG) with 8-bit immediate ("literal") operand. E.g. movlw (move literal to WREG), andlw (AND literal with WREG). One instruction peculiar to the PIC is retlw, load immediate into WREG and return, which is used with computed branches to produce lookup tables.
Operation with WREG and indexed register. The result can be written to either the Working register (e.g. addwf reg,w). or the selected register (e.g. addwf reg,f).
Bit operations. These take a register number and a bit number, and perform one of 4 actions: set or clear a bit, and test and skip on set/clear. The latter are used to perform conditional branches. The usual ALU status flags are available in a numbered register so operations such as "branch on carry clear" are possible.
Control transfers. Other than the skip instructions previously mentioned, there are only two: goto and call.
A few miscellaneous zero-operand instructions, such as return from subroutine, and sleep to enter low-power mode.
Performance
The architectural decisions are directed at the maximization of speed-to-cost ratio. The PIC architecture was among the first scalar CPU designs,[citation needed] and is still among the simplest and cheapest. The Harvard architecture—in which instructions and data come from separate sources—simplifies timing and microcircuit design greatly, and this benefits clock speed, price, and power consumption.
The PIC instruction set is suited to implementation of fast lookup tables in the program space. Such lookups take one instruction and two instruction cycles. Many functions can be modeled in this way. Optimization is facilitated by the relatively large program space of the PIC (e.g. 4096 × 14-bit words on the 16F690) and by the design of the instruction set, which allows for embedded constants. For example, a branch instruction's target may be indexed by W, and execute a "RETLW" which does as it is named - return with literal in W.
Interrupt latency is constant at three instruction cycles. External interrupts have to be synchronized with the four clock instruction cycle, otherwise there can be a one instruction cycle jitter. Internal interrupts are already synchronized. The constant interrupt latency allows PICs to achieve interrupt driven low jitter timing sequences. An example of this is a video sync pulse generator. This is no longer true in the newest PIC models, because they have a synchronous interrupt latency of three or four cycles.
Advantages
The PIC architectures have these advantages:
Small instruction set to learn
RISC architecture
Built in oscillator with selectable speeds
Easy entry level, in circuit programming plus in circuit debugging PICKit units available for less than $50
Inexpensive microcontrollers
Wide range of interfaces including I²C, SPI, USB, USART, A/D, programmable comparators, PWM, LIN, CAN, PSP, and Ethernet[8]
Limitations
The PIC architectures have these limitations:
One accumulator
Register-bank switching is required to access the entire RAM of many devices
Operations and registers are not orthogonal; some instructions can address RAM and/or immediate constants, while others can only use the accumulator
The following stack limitations have been addressed in the PIC18 series, but still apply to earlier cores:
The hardware call stack is not addressable, so preemptive task switching cannot be implemented
Software-implemented stacks are not efficient, so it is difficult to generate reentrant code and support local variables
With paged program memory, there are two page sizes to worry about: one for CALL and GOTO and another for computed GOTO (typically used for table lookups). For example, on PIC16, CALL and GOTO have 11 bits of addressing, so the page size is 2048 instruction words. For computed GOTOs, where you add to PCL, the page size is 256 instruction words. In both cases, the upper address bits are provided by the PCLATH register. This register must be changed every time control transfers between pages. PCLATH must also be preserved by any interrupt handler.[9]
Compiler development
While several commercial compilers are available, in 2008, Microchip released their own C compilers, C18 and C30, for the line of 18F 24F and 30/33F processors.
The easy to learn RISC instruction set of the PIC assembly language code can make the overall flow difficult to comprehend. Judicious use of simple macros can increase the readability of PIC assembly language. For example, the original Parallax PIC assembler ("SPASM") has macros which hide W and make the PIC look like a two-address machine. It has macro instructions like "mov b, a" (move the data from address a to address b) and "add b, a" (add data from address a to data in address b). It also hides the skip instructions by providing three operand branch macro instructions such as "cjne a, b, dest" (compare a with b and jump to dest if they are not equal).
Family core architectural differences
PICmiro chips have a Harvard architecture, and instruction words are unusual sizes. Originally, 12-bit instructions included 5 address bits to specify the memory operand, and 9-bit branch destinations. Later revisions added opcode bits, allowing additional address bits.
Baseline core devices (12 bit)
These devices feature a 12-bit wide code memory, a 32-byte register file, and a tiny two level deep call stack. They are represented by the PIC10 series, as well as by some PIC12 and PIC16 devices. Baseline devices are available in 6-pin to 40-pin packages.
Generally the first 7 to 9 bytes of the register file are special-purpose registers, and the remaining bytes are general purpose RAM. Pointers are implemented using a register pair: after writing an address to the FSR (file select register), the INDF (indirect f) register becomes an alias for the addressed register. If banked RAM is implemented, the bank number is selected by the high 3 bits of the FSR. This affects register numbers 16–31; registers 0–15 are global and not affected by the bank select bits.
Because of the very limited register space (5 bits), 4 rarely read registers were not assigned addresses, but written by special instructions (OPTION and TRIS).
The ROM address space is 512 words (12 bits each), which may be extended to 2048 words by banking. CALL and GOTO instructions specify the low 9 bits of the new code location; additional high-order bits are taken from the status register. Note that a CALL instruction only includes 8 bits of address, and may only specify addresses in the first half of each 512-word page.
Lookup tables are implemented using a computed GOTO (assignment to PCL register) into a table of RETLW instructions.
The instruction set is as follows. Register numbers are referred to as "f", while constants are referred to as "k". Bit numbers (0–7) are selected by "b". The "d" bit selects the destination: 0 indicates W, while 1 indicates that the result is written back to source register f. The C and Z status flags may be set based on the result; otherwise they are unmodified. Add and subtract (but not rotate) instructions that set C also set the DC (digit carry) flag, the carry from bit 3 to bit 4, which is useful for BCD arithmetic.</div>
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